1. Technical Field
The present invention relates to semiconductor integrated circuits, and more particularly, to a self-refresh test circuit of a semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus stores the value of data as a voltage level stored in a capacitor. Due to current leakage of the capacitor, the voltage stored in the capacitor cannot be maintained at the same voltage level. Therefore, the semiconductor memory apparatus is required to perform a refresh operations periodically to maintain the voltage level held by the capacitor.
The semiconductor memory apparatus operates in an auto-refresh mode or self-refresh mode. In the auto-refresh mode, a refresh operation is performed in accordance with an external command. In the self-refresh mode, a refresh operation is performed in accordance with an internal command of the semiconductor memory apparatus.
FIG. 1 is a configuration diagram of a self-refresh pulse control unit of a conventional semiconductor memory apparatus. Referring to FIG. 1, the self-refresh pulse control unit 10 outputs a self-refresh period signal ‘SRF_ps’ as a self-refresh pulse ‘P_srf’ when a self-refresh exit signal ‘SRF_exit’ is disabled. When the self-refresh exit signal ‘SRF_exit’ is enabled, the self-refresh pulse control unit 10 fixes the self-refresh pulse ‘P_srf’ to a specific level. In this case, the self-refresh period signal ‘SRF_ps’ is a signal which is synchronized with a clock signal to be enabled every predetermined period, and the self-refresh exit signal ‘SRF_exit’ is a signal which is inputted from the outside of the semiconductor memory apparatus and is not is synchronized with a clock signal.
When the semiconductor memory apparatus enters the self-refresh mode, the self-refresh pulse control unit 10 outputs the self-refresh pulse ‘P_srf’ which is enabled every predetermined period. When the self-refresh exit signal ‘SRF_exit’ is enabled in an enable interval of the self-refresh period signal ‘SRF_ps’, the self-refresh pulse ‘P_srf’ is disabled. At this time, the self-refresh pulse ‘P_srf’ has an enable interval shorter than a set enable interval, and the signal or pulse having a shorter enable interval than the set enable interval is referred to as a glitch signal or pulse. A glitch signal or pulse, such as this, may cause a malfunction of the semiconductor memory apparatus.
To test whether or not the semiconductor memory apparatus malfunctions when the self-refresh pulse ‘P_srf’ is generated as a glitch pulse, a test of enabling the self-refresh exit signal ‘SRF_exit’ in the enable interval of the self-refresh period signal ‘SRF_ps’ is repeated.
Semiconductor memory apparatuses are known to be susceptible to changes in process, voltage, and temperature (P.V.T.) that the respective semiconductor memory apparatuses have different self-refresh periods. Therefore, since it is difficult to find an enable interval of the self-refresh period signal ‘SRF_ps’, the test time increases.